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| M16C/62 Group (M16C/62P) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0001-0110Z Rev.1.10 2003.05.28 Overview The M16C/62 group (M16C/62P) of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations. Applications Audio, cameras, office/communications/portable/industrial equipment, etc Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. Rev.1.10 2003.05.28 page 1 of 61 M16C/62 Group (M16C/62P) Overview Performance Outline Table 1.1.1 lists performance outline of M16C/62P group. Table 1.1.1. Performance outline of M16C/62P group Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 41.7 ns (f(BCLK)= 24MHZ, VCC1= 3.0V to 5.5V) 100 ns (f(BCLK)= 10MHZ, VCC1= 2.7V to 5.5V) Memory ROM (See the product list) capacity RAM (See the product list) I/O port 100-pin version 8 bits x 10, 7 bits x 1 P0 to P5: VCC2 ports P6 to P10: VCC1 ports P0 to P10 (except P85) 8 bits x 13, 7 bits x 1, P0 to P5, P12, P13: VCC2 ports 128-pin version P0 to P14 (except P85) 2 bits x 1 _______ P6 to P10, P11, P14: VCC1 ports Input port P85 1 bit x 1 (NMI pin level judgment): VCC1 ports Multifunction timer Output 16 bits x 5 channels (TA0, TA1, TA2, TA3, TA4) Input 16 bits x 6 channels (TB0, TB1, TB2, TB3, TB4, TB5) Serial I/O 3 channels (UART0, UART1, UART2) UART, clock synchronous, I2C bus1 (option4), or IEBus2 (option4) 2 channels (SI/O3, SI/O4) Clock synchronous A-D converter 10 bits x (8 x 3 + 2) channels D-A converter 8 bits x 2 DMAC 2 channels (trigger: 25 sources) CRC calculation circuit CRC-CCITT Watchdog timer 15 bits x 1 (with prescaler) Interrupt 29 internal and 8 external sources, 4 software sources, 7 levels Clock generation circuit 4 circuits * Main clock (These circuits contain a built-in feedback * Sub-clock resistor and external ceramic/quartz oscillator) * Ring oscillator(main-clock oscillation stop detect function) * PLL frequency synthesizer Voltage detection circuit Present (option4) Power supply voltage VCC1=3.0V to 5.5V, VCC2=3.0V to VCC1(f(BCLK)=24MHZ) VCC1=VCC2=2.7V to 5.5V (f(BCLK)=10MHZ) Flash memory Program/erase voltage 3.3V 0.3V or 5.0V 0.5V Number of program/erase 100 times, 10000 times3 (option4) Power consumption 14mA (VCC1=VCC2=5V, f(BCLK)=24MHZ) 8mA (VCC1=VCC2=3V, f(BCLK)=10MHZ) 1.8A (VCC1=VCC2=3V, f(XCIN)=32kHZ, when wait mode) I/O I/O withstand voltage 5.0V characteristics Output current 5mA Memory expansion Available (to 4M bytes) Operating ambient temperature -20 to 85C -40 to 85C (option4) Device configuration CMOS high performance silicon gate Package 100-pin and 128-pin plastic mold QFP Notes: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. Block 1 and block A are a 10,000 times of programming and erasure. All other blocks are guaranteed of 1,000 times of programming and erasure. (Under development; mass production scheduled to start in the 3rd quarter of 2003) 4. If you desire this option, please so specify. Rev.1.10 2003.05.28 page 2 of 61 M16C/62 Group (M16C/62P) Overview Block Diagram Figure 1.1.1 is a block diagram of the M16C/62P group. 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 8 Internal peripheral functions Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit A-D converter (10 bits X 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O System clock generator XIN-XOUT XCIN-XCOUT PLL frequency synthesizer Ring oscillator Port P8 7 (8 bits X 3 channels) CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) Clock synchronous serial I/O (8 bits X 2 channels) Port P85 Watchdog timer (15 bits) M16C/60 series16-bit CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC Memory ROM (Note 1) RAM (Note 2) Port P9 DMAC (2 channels) 8 D-A converter (8 bits X 2 channels) Port P10 FLG Multiplier 8 (Note 3) (Note 3) Port P14 (Note 3) Port P13 (Note 3) 8 2 8 8 Note 1: ROM size depends on microcomputer type. Note 2: RAM size depends on microcomputer type. Note 3: Ports P11 to P14 exist only in 128-pin version. Figure 1.1.1. Block Diagram Rev.1.10 2003.05.28 page 3 of 61 M16C/62 Group (M16C/62P) Overview Product List Tables 1.1.2 and 1.1.3 list the M16C/62P group products and Figure 1.1.2 shows the type numbers, memory sizes and packages. Table 1.1.2. Product List (1) Type No. M30622M6P-XXXFP M30622M6P-XXXGP M30622M8P-XXXFP M30622M8P-XXXGP M30622MAP-XXXFP M30622MAP-XXXGP M30620MCP-XXXFP M30620MCP-XXXGP M30622MEP-XXXFP M30622MEP-XXXGP M30623MEP-XXXGP M30622MGP-XXXFP M30622MGP-XXXGP M30623MGP-XXXGP M30624MGP-XXXFP M30624MGP-XXXGP M30625MGP-XXXGP M30622MWP-XXXFP M30622MWP-XXXGP M30623MWP-XXXGP M30624MWP-XXXFP M30624MWP-XXXGP M30625MWP-XXXGP M30626MWP-XXXFP M30626MWP-XXXGP M30627MWP-XXXGP M30622MHP-XXXFP M30622MHP-XXXGP M30623MHP-XXXGP M30624MHP-XXXFP M30624MHP-XXXGP M30625MHP-XXXGP M30626MHP-XXXFP M30626MHP-XXXGP M30627MHP-XXXGP : Under development : Under planning 31K bytes 384K bytes 24K bytes 16K bytes 31K bytes 320K bytes 24K bytes 16K bytes 256K bytes 20K bytes 12K bytes 192K bytes 12K bytes ROM capacity 48K bytes RAM capacity 4K bytes Package type 100P6S-A 100P6Q-A 64K bytes 96K bytes 128K bytes 100P6S-A 4K bytes 5K bytes 10K bytes 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A MASK ROM version As of April 2003 Remarks Rev.1.10 2003.05.28 page 4 of 61 M16C/62 Group (M16C/62P) Overview Table 1.1.3. Product List (2) Type No. M30622F8PFP M30622F8PGP M30620FCPFP M30620FCPGP M30624FGPFP M30624FGPGP M30625FGPGP M30626FHPFP M30626FHPGP M30627FHPGP M30626FJPFP M30626FJPGP M30627FJPGP M30620SPFP M30620SPGP M30622SPFP M30622SPGP : Under development : Under planning 4K bytes 10K bytes 512K bytes 31K bytes 384K bytes 31K bytes 256K bytes 20K bytes 128K bytes 10K bytes 64K bytes ROM capacity RAM capacity 4K bytes Package type 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A As of April 2003 Remarks Flash memory version External ROM version Type No. M 3 0 6 2 6 M H P- X X X F P Package type: FP : Package GP : Package 100P6S-A 100P6Q-A, 128P6Q-A ROM No. Omitted for flash memory version and external ROM version ROM capacity: 6: 48K bytes 8: 64K bytes A: 96K bytes C: 128K bytes E: 192K bytes G: 256K bytes W: 320K bytes H: 384K bytes J: 512K bytes Memory type: M: Mask ROM version F: Flash memory version S: External ROM version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/62 Group M16C Family Figure 1.1.2. Type No., Memory Size, and Package Rev.1.10 2003.05.28 page 5 of 61 M16C/62 Group (M16C/62P) Overview Pin Configuration Figures 1.1.3 to 1.1.5 show the pin configurations (top view). PIN CONFIGURATION (top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/AN20/A0(/D0/-) P21/AN21/A1(/D1/D0) P22/AN22/A2(/D2/D1) P23/AN23/A3(/D3/D2) P24/AN24/A4(/D4/D3) P25/AN25/A5(/D5/D4) P26/AN26/A6(/D6/D5) P27/AN27/A7(/D7/D6) VSS P30/A8(/-/D7) VCC2 P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC P97/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 45 M16C/62P Group 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0/SCL0 P63/TXD0/SDA0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1/SCL1 P67/TXD1/SDA1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC1 P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL2/TA0IN/TB5IN(Note) P70/TXD2/SDA2/TA0OUT(Note) Package: 100P6S-A Note: P70 and P71 are N channel open-drain output pins. Figure 1.1.3. Pin Configuration (Top View) Rev.1.10 2003.05.28 page 6 of 61 M16C/62 Group (M16C/62P) Overview PIN CONFIGURATION (top view) P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/AN20/A0(/D0/-) P21/AN21/A1(/D1/D0) P22/AN22/A2(/D2/D1) P23/AN23/A3(/D3/D2) P24/AN24/A4(/D4/D3) P25/AN25/A5(/D5/D4) P26/AN26/A6(/D6/D5) P27/AN27/A7(/D7/D6) VSS P30/A8(/-/D7) VCC2 P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P12/D10 P11/D9 P10/D8 P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 M16C/62P Group P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0/SCL0 P63/TXD0/SDA0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1/SCL1 P67/TXD1/SDA1 P70/TXD2/SDA2/TA0OUT(Note) P71/RxD2/SCL2/TA0IN/TB5IN(Note) P72/CLK2/TA1OUT/V P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC1 P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V Package: 100P6Q-A Note: P70 and P71 are N channel open-drain output pins. Figure 1.1.4. Pin Configuration (Top View) Rev.1.10 2003.05.28 page 7 of 61 M16C/62 Group (M16C/62P) Overview PIN CONFIGURATION (top view) P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/AN20/A0(/D0/-) P21/AN21/A1(/D1/D0) P22/AN22/A2(/D2/D1) P23/AN23/A3(/D3/D2) P24/AN24/A4(/D4/D3) P25/AN25/A5(/D5/D4) P26/AN26/A6(/D6/D5) P27/AN27/A7(/D7/D6) VSS P30/A8(/-/D7) VCC2 P120 P121 P122 P123 P124 P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P10/D8 P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 P117 P116 P115 P114 P113 P112 P111 P110 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 23 45 M16C/62P Group P125 P126 P127 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P130 P131 P132 P133 P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P134 P135 P136 P137 P60/CTS0/RTS0 P61/CLK0 P62/RxD0/SCL0 P63/TXD0/SDA0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 VSS 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VREF AVCC P97/ADTRG/SIN4 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 P141 P140 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC1 P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL2/TA0IN/TB5IN(Note) P70/TXD2/SDA2/TA0OUT(Note) P67/TXD1/SDA1 VCC1 P66/RxD1/SCL1 Package: 128P6Q-A Note: P70 and P71 are N channel open-drain output pins. Figure 1.1.5. Pin Configuration (Top View) Rev.1.10 2003.05.28 page 8 of 61 M16C/62 Group (M16C/62P) Overview Table 1.1.4 Pin Description (100-pin and 128-pin Packages) Pin name Signal name I/O type Power supply Function Apply 2.7V to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The Vcc apply condition is that VCC2 VCC1 (Note) VCC1, VCC2, Power supply VSS input CNVSS CNVSS Input VCC1 This pin switches between processor modes. Connect this pin to VSS pin when after a reset you want to start operation in singlechip mode (memory expansion mode) or the VCC1 pin when starting operation in microprocessor mode. "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit input/ output. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an external data bus. A 16-bit width is selected when this input is "L"; an 8-bit width is selected when this input is "H". This input must be fixed to either "H" or "L". Connect this pin to the VSS pin when operating in single-chip mode. This pin is a power supply input for the A-D converter. Connect this pin to VCC1. This pin is a power supply input for the A-D converter. Connect this pin to VSS. This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. This port has an input/output select direction register, allowing each pin in that port to be directed for input or output individually. If any port is set for input, selection can be made for it in a program whether or not to have a pull-up resistor in 4 bit units. This selection is unavailable in memory extension and microprocessor modes. This port can function as input pins for the A-D converter when so selected in a program. When set as a separate bus, these pins input and output data (D0 -D7). This is an 8-bit I/O port equivalent to P0. P15 to P17 also function as INT interrupt input pins as selected by a program. When set as a separate bus, these pins input and output data (D8 -D15). RESET XIN XOUT BYTE Reset input Clock input Input Input VCC1 VCC1 Clock output Output External data Input bus width select input Analog power supply input Analog power supply input Input Reference voltage input Input/output VCC2 AVCC AVSS VREF P00 to P07 I/O port P0 D0 to D7 P10 to P17 I/O port P1 D8 to D15 P20 to P27 I/O port P2 A0 to A7 A0/D0 to A7/D7 A0 A1/D0 to A7/D6 P30 to P37 I/O port P3 A8 to A15 A8/D7, A9 to A15 Input/output Input/output VCC2 Input/output Input/output VCC2 Output Input/output This is an 8-bit I/O port equivalent to P0. This port can function as input pins for the A-D converter when so selected in a program. These pins output 8 low-order address bits (A0 to A7). If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0 to D7) and output 8 low-order address bits (A0 to A7) separated in time by multiplexing. If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D0 to D6) and output address (A1 to A7) separated in time by multiplexing. They also output address (A0). This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A8 to A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A9 to A15). This is an 8-bit I/O port equivalent to P0. These pins output A16 to A19 and CS0 to CS3 signals. A16 to A19 are 4 high- order address bits. CS0 to CS3 are chip select signals used to specify an access space. Output Input/output Input/output VCC2 Output Input/output Output P40 to P47 I/O port P4 A16 to A19, CS0 to CS3 Input/output VCC2 Output Output Note: In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. Rev.1.10 2003.05.28 page 9 of 61 M16C/62 Group (M16C/62P) Overview Table 1.1.5 Pin Description (100-pin and 128-pin Packages) (Continued) Pin name P50 to P57 Signal name I/O port P5 I/O type Power supply Function This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by program. Output WRL/WR, WRH/BHE, RD, BCLK, HLDA, and ALE signals. WRL/WR and WRH/BHE are switchable in a program. Note that WRL and WRH are always used as a pair, so as WR and BHE. WRL, WRH, and RD selected If the external data bus is 16 bits wide, data are written to even addresses when the WRL signal is low, and written to odd addresses when the WRH signal is low. Data are read out when the RD signal is low. WR, BHE, and RD selected Data are written when the WR signal is low, or read out when the RD signal is low. Odd addresses are accessed when the BHE signal is low. Use this mode when the external data bus is 8 bits wide. The microcomputer goes to a hold state when input to the HOLD pin is held low. While in the hold state, HLDA outputs a low level. ALE is used to latch the address. While the input level of the RDY pin is low, the bus of the microcomputer goes to a wait state. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as UART0 and UART1 I/O pins as selected by program. This is an 8-bit I/O port equivalent to P0 (P70 and P71 are N channel open-drain output). This port can function as input/output pins for timers A0 to A3 when so selected in a program. Furthermore, P70 to P75, P71, and P72 to P75 can also function as input/output pins for UART2, an input pin for timer B5, and output pins for the three-phase motor control timer, respectively. P80 to P84, P86, and P87 are I/O ports with the same functions as P0. When so selected in a program, P80 to P81 and P82 to P84 can function as input/output pins for timer A4 or output pins for the three-phase motor control timer and INT interrupt input pins, respectively. P86 and P87, when so selected in a program, both can function as input/output pins for the subclock oscillator circuit. In that case, connect a crystal resonator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port shared with NMI. An NMI interrupt request is generated when input on this pin changes state from high to low. The NMI function cannot be disabled in a program. A pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SI/O3 and SI/O4 I/O pins, Timer B0 to B4 input pins, DA converter output pins, A-D converter input pins, or A-D trigger input pins as selected by program. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as A-D converter input pins as selected by program. Furthermore, P104 to P107 also function as input pins for the key input interrupt function. Input/output VCC2 WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY Output Output Output Output Output Input Output Input P60 to P67 P70 to P77 I/O port P6 I/O port P7 Input/output VCC1 Input/output VCC1 P80 to P84, I/O port P8 P86, P87, P85 I/O port P85 Input/output VCC1 Input/output Input/output Input P90 to P97 I/O port P9 Input/output VCC1 P100 to P107 I/O port P10 Input/output VCC1 Table 1.1.6 Pin Description (128-pin Package) Pin name Signal name I/O type Power supply circuit block Function This is an 8-bit I/O port equivalent to P0. This is an 8-bit I/O port equivalent to P0. This is an 8-bit I/O port equivalent to P0. This is an 2-bit I/O port equivalent to P0. P110 to P117 I/O port P11 Input/output VCC1 P120 to P127 I/O port P12 Input/output VCC2 P130 to P137 I/O port P13 Input/output VCC2 P140, P141 I/O port P14 Input/output VCC1 Rev.1.10 2003.05.28 page 10 of 61 M16C/62 Group (M16C/62P) Memory Memory Figure 1.2.1 is a memory map of the M16C/62P group. The address space extends the 1M bytes from address 0000016 to FFFFF16. The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example, a 64-Kbyte internal ROM is allocated to the addresses from F000016 to FFFFF16. The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 0040016. For example, a 10-Kbytes internal RAM is allocated to the addresses from 0040016 to 02BFF16. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used by the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software Manual." In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. 0000016 SFR 0040016 Internal RAM XXXXX16 Internal RAM Size 4K bytes 5K bytes 10K bytes 12K bytes 16K bytes 20K bytes 24K bytes 31K bytes Address XXXXX16 013FF16 017FF16 02BFF16 033FF16 043FF16 053FF16 063FF16 07FFF16 Size 48K bytes 64K bytes 96K bytes 128K bytes 192K bytes 256K bytes 320K bytes 384K bytes 512K bytes Internal ROM Address YYYYY16 F400016 F000016 E800016 E000016 D000016 C000016 B000016 A000016 8000016 FFE0016 Reserved area (Note 1) 1000016 2700016 Special page vector table External area Reserved area 2800016 External area 8000016 Reserved area YYYYY16 (Note 2) FFFDC16 Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset Internal ROM FFFFF16 FFFFF16 Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: In memory expansion mode, can not be used. Note 3: Shown here is a memory map for the case where the PM10 bit in the PM1 register is "1" and the PM13 bit in the PM1 register is "1". Figure 1.2.1. Memory Map Rev.1.10 2003.05.28 page 11 of 61 M16C/62 Group (M16C/62P) Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R3 R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits)R1L(R1's low bits) R2 R3 A0 A1 FB Address registers (Note) Frame base registers (Note) b0 Data registers (Note) b19 b15 INTBH INTBL Interrupt table register The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC b15 b0 Program counter USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OB SZ DC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Note: These registers comprise a register bank. There are two register banks. Figure 1.3.1. Central Processing Unit Register (1) Data Registers (R0, R1, R2 and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0. (2) Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev.1.10 2003.05.28 page 12 of 61 M16C/62 Group (M16C/62P) Central Processing Unit (CPU) (3) Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. (4) Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. (5) Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. (6) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. (7) Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. (8) Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. * Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0". * Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". * Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". * Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". * Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted. * Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. * Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. * Reserved Area When write to this bit, write "0". When read, its content is indeterminate. Rev.1.10 2003.05.28 page 13 of 61 M16C/62 Group (M16C/62P) SFR Register Symbol After reset Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Chip select control register Address match interrupt enable register Protect register Data bank register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 (Note 2) PM0 PM1 CM0 CM1 CSR AIER PRCR DBR CM2 WDTS WDC RMAD0 000000002(CNVSS pin is "L") 000000112(CNVSS pin is "H") (Note 3) 000010002 010010002 001000002 000000012 XXXXXX002 XX0000002 0016 0000X0002 XX16 00XXXXXX2(Note 4) 0016 0016 X016 0016 0016 X016 Address match interrupt register 1 RMAD1 Voltage detection register 1 Voltage detection register 2 Chip select expansion control register PLL control register 0 Processor mode register 2 Voltage down detection interrupt register DMA0 source pointer (Note 5) (Note 5) VCR1 VCR2 CSE PLC0 PM2 D4INT SAR0 000010002 0016 0016 0001X0102 XXX000002 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 DMA0 destination pointer DAR0 DMA0 transfer counter TCR0 DMA0 control register DM0CON 00000X002 DMA1 source pointer SAR1 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 DMA1 destination pointer DAR1 DMA1 transfer counter TCR1 DMA1 control register DM1CON 00000X002 Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. Note 4: The WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program. It is set to "0" when the input voltage at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to "1" (RAM retention limit detection circuit enable Note 5: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. X : Nothing is mapped to this bit Rev.1.10 2003.05.28 page 14 of 61 M16C/62 Group (M16C/62P) SFR Register Symbol After reset Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 INT3 interrupt control register Timer B5 interrupt control register Timer B4 interrupt control register, UART1 BUS collision detection interrupt control register Timer B3 interrupt control register, UART0 BUS collision detection interrupt control register INT3IC TB5IC TB4IC, U1BCNIC TB3IC, U0BCNIC SI/O4 interrupt control register (S4IC), INT5 interrupt control register SI/O3 interrupt control register, INT4 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A-D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XX00X0002 Note :The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.1.10 2003.05.28 page 15 of 61 M16C/62 Group (M16C/62P) SFR Register Symbol After reset Address 008016 008116 008216 008316 008416 008516 008616 ~ 01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16 ~ Flash identification register Flash memory control register 1 Flash memory control register 0 Address match interrupt register 2 (Note 2) (Note 2) (Note 2) FIDR FMR1 FMR0 RMAD2 XXXXXX002 0X00XX0X2 XX0000012 0016 0016 X016 XXXXXX002 0016 0016 X016 Address match interrupt enable register 2 Address match interrupt register 3 AIER2 RMAD3 ~ 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16 ~ Peripheral clock select register PCLKR 000000112 ~ 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 ~ Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: This register is included in the flash memory version. X : Nothing is mapped to this bit Rev.1.10 2003.05.28 page 16 of 61 M16C/62 Group (M16C/62P) SFR Register Symbol TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 After reset 000XXXXX2 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 XX16 XX16 Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Timer B3, 4, 5 count start flag Timer A1-1 register Timer A2-1 register Timer A4-1 register Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt occurrence frequency set counter Timer B3 register Timer B4 register Timer B5 register TB3 TB4 TB5 XX16 XX16 XX16 XX16 XX16 XX16 Timer B3 mode register Timer B4 mode register Timer B5 mode register Interrupt cause select register 2 Interrupt cause select register SI/O3 transmit/receive register SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register SI/O4 control register SI/O4 bit rate generator TB3MR TB4MR TB5MR IFSR2A IFSR S3TRR S3C S3BRG S4TRR S4C S4BRG 00XX00002 00XX00002 00XX00002 00XXXXXX2 0016 XX16 010000002 XX16 XX16 010000002 XX16 UART0 special mode register 4 UART0 special mode register 3 UART0 special mode register 2 UART0 special mode register UART1 special mode register 4 UART1 special mode register 3 UART1 special mode register 2 UART1 special mode register UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 0016 000X0X0X2 X00000002 X00000002 0016 000X0X0X2 X00000002 X00000002 0016 000X0X0X2 X00000002 X00000002 0016 XX16 XXXXXXXX2 XXXXXXXX2 000010002 000000102 XXXXXXXX2 XXXXXXXX2 Note : The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.1.10 2003.05.28 page 17 of 61 M16C/62 Group (M16C/62P) SFR Register Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON After reset 0016 0XXXXXXX2 0016 0016 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 0016 00XX00002 00XX00002 00XX00002 XXXXXX002 0016 XX16 XXXXXXXX2 XXXXXXXX2 000010002 000000102 XXXXXXXX2 XXXXXXXX2 0016 XX16 XXXXXXXX2 XXXXXXXX2 000010002 000000102 XXXXXXXX2 XXXXXXXX2 X00000002 Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register UART0 transmit/receive mode register UART0 bit rate generator UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 bit rate generator UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register UART transmit/receive control register 2 DMA0 request cause select register DMA1 request cause select register CRC data register CRC input register DM0SL DM1SL CRCD CRCIN 0016 0016 XX16 XX16 XX16 Note : The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.1.10 2003.05.28 page 18 of 61 M16C/62 Group (M16C/62P) SFR Register Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After reset XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 A-D control register 2 A-D control register 0 A-D control register 1 D-A register 0 D-A register 1 D-A control register Port P14 control register Pull-up control register 3 Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P11 register Port P10 direction register Port P11 direction register Port P12 register Port P13 register Port P12 direction register Port P13 direction register Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register ADCON2 ADCON0 ADCON1 DA0 DA1 DACON PC14 PUR3 P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 PUR0 PUR1 PUR2 PCR 0016 00000XXX2 0016 XX16 XX16 0016 XX00XXXX2 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 00X000002 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 0016 000000002 000000102 (Note 2) 0016 0016 Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: At hardware reset 1 or hardware reset 2, the register is as follows: * "000000002" where "L" is inputted to the CNVSS pin * "000000102" where "H" is inputted to the CNVSS pin At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: * "000000002" where the PM01 to PM00 bits in the PM0 register are "002" (single-chip mode) * "000000102" where the PM01 to PM00 bits in the PM0 register are "012" (memory expansion mode) or "112" (microprocessor mode) X : Nothing is mapped to this bit Rev.1.10 2003.05.28 page 19 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics Electrical Characteristics Table 1.5.1. Absolute Maximum Ratings Symbol VCC1, VCC2 VCC2 AVCC Supply voltage Supply voltage Analog supply voltage Input voltage RESET, CNVSS, BYTE, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P140, P141, VREF, XIN P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P120 to P127, P130 to P137 P70, P71 Output voltage VO P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, P110 to P117, P140, P141, XOUT P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P120 to P127, P130 to P137 P70, P71 Pd Topr Tstg Power dissipation Operating ambient temperature Storage temperature Topr=25 C -0.3 to 6.5 300 -20 to 85 / -40 to 85 -65 to 150 V mW C C Parameter Condition VCC1=AVCC VCC2 VCC1=AVCC Rated value -0.3 to 6.5 -0.3 to VCC1+0.1 -0.3 to 6.5 Unit V V V -0.3 to VCC1+0.3 V VI -0.3 to VCC2+0.3 V -0.3 to 6.5 V -0.3 to VCC1+0.3 V -0.3 to VCC2+0.3 V Rev.1.10 2003.05.28 page 20 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics Table 1.5.2. Recommended Operating Conditions (Note 1) Symbol VCC1, VCC2 AVcc Vss AVss Supply voltage(VCC1VCC2) Analog supply voltage Supply voltage HIGH input voltage VIH Analog supply voltage P31 to P37, P40 to P47, P50 to P57, P120 to P127, P130 to P137 P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input during memory expansion and microprocessor modes) P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P140, P141, XIN, RESET, CNVSS, BYTE P70 , P71 LOW input P31 to P37, P40 to P47, P50 to P57, P120 to P127, P130 to P137 voltage P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) VIL P00 to P07, P10 to P17, P20 to P27, P30 (data input during memory expansion and microprocessor modes) P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P140, P141, XIN, RESET, CNVSS, BYTE HIGH peak output P00 to P07, P10 to P17, P20 to P27,P30 to P37, current P40 to P47, P50 to P57, P60 to P67,P72 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140, P141 P00 to P07, P10 to P17, P20 to P27,P30 to P37, HIGH average output current P40 to P47, P50 to P57, P60 to P67,P72 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140, P141 P00 to P07, P10 to P17, P20 to P27,P30 to P37, LOW peak output current P40 to P47, P50 to P57, P60 to P67,P70 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140, P141 P00 to P07, P10 to P17, P20 to P27,P30 to P37, LOW average P40 to P47, P50 to P57, P60 to P67,P70 to P77, output current P80 to P84,P86,P87,P90 to P97,P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140, P141 VCC1=3.0 to 5.5V Main clock input oscillation frequency (Note 4) VCC1=2.7 to 3.0V Sub-clock oscillation frequency Ring oscillation frequency PLL clock oscillation frequency (Note 4) VCC1=3.0 to 5.5V VCC1=2.7 to 3.0V f (BCLK) TSU(PLL) CPU operation clock PLL frequency synthesizer stabilization wait time VCC1=5.0V VCC1=3.0V 10 10 0 0.8VCC2 0.8VCC2 0.5VCC2 0.8VCC1 0.8VCC1 0 0 0 Parameter Min. 2.7 Standard Typ. 5.0 VCC1 0 0 Max. 5.5 Unit V V V VCC2 VCC2 VCC2 VCC1 6.5 0.2VCC2 0.2VCC2 0.16VCC2 V V V V V V V V V V 0 0.2VCC1 I OH (peak) -10.0 mA I OH (avg) - 5 .0 mA I OL (peak) 10.0 mA I OL (avg) 5.0 mA f (XIN) f (XCIN) f (Ring) f (PLL) 0 0 32.768 1 16 20 X VCC1-44 50 24 46.67 X VCC1116 24 20 50 MHz MHz kHz MHz MHz MHz MHz ms ms Note 1: Referenced to VCC = VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. Note 2: The mean output current is the mean value within 100ms. Note 3: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P140 and P141 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, P80 to P84, P12, and P13 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2 must be -40mA max. The total IOH (peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH (peak) for ports P6, P7, and P80 to P84 must be -40mA max. The total IOH (peak) for ports P86, P87, P9, P10, P11, P140, and P141 must be -40mA max. Note 4: Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage. f(XIN) operating maximum frequency [MHZ] f(PLL) operating maximum frequency [MHZ] Main clock input oscillation frequency 20 x VCC1-44MHZ 16.0 PLL clock oscillation frequency 46.67 x VCC1-116MHZ 24.0 10.0 10.0 0.0 2.7 3.0 5.5 VCC1[V] (main clock: no division) 0.0 2.7 3.0 5.5 VCC1[V] (PLL clock oscillation) Rev.1.10 2003.05.28 page 21 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics Table 1.5.3. A-D Conversion Characteristics (Note 1) Symbol - Resolution Parameter Measuring condition VREF =VCC1 AN0 to AN7 input VREF= ANEX0, ANEX1 input VCC1= External operation amp 5V connection mode AN00 to AN07 input AN20 to AN27 input VREF= VCC1= 3.3V AN0 to AN7 input ANEX0, ANEX1 input External operation amp connection mode AN00 to AN07 input AN20 to AN27 input Standard Unit Min. Typ. Max. 10 3 7 Bits LSB LSB INL Integral nonlinearity error 10 bit 5 7 LSB LSB 8 bit - Absolute accuracy 10 bit VREF =VCC1=3.3V AN0 to AN7 input VREF= ANEX0, ANEX1 input VCC1= External operation amp 5V connection mode AN00 to AN07 input AN20 to AN27 input VREF= VCC1= 3.3V AN0 to AN7 input ANEX0, ANEX1 input External operation amp connection mode AN00 to AN07 input AN20 to AN27 input 2 3 7 LSB LSB LSB 5 7 LSB LSB DNL - - RLADDER tCONV tCONV tSAMP VREF VIA 8 bit Differential non-linearity error Offset error Gain error Ladder resistance Conversion time(10bit), Sample & hold function available Conversion time(8bit), Sample & hold function available Sampling time Reference voltage Analog input voltage VREF =VCC1=3.3V VREF =VCC1 VREF =VCC1=5V, oAD=10MHz VREF =VCC1=5V, oAD=10MHz 10 3.3 2.8 0.3 2.0 0 2 1 3 3 40 LSB LSB LSB LSB k s s s V V VCC1 VREF Note 1: Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. Note 2: If VCC1 > VCC2, do not use AN00 to AN07 and AN20 to AN27 as analog input pins. Note 3: AD operation clock frequency (OAD frequency) must be 10 MHz or less. And divide the fAD if VCC1 is less than 4.2V, and make OAD frequency equal to or lower than fAD/2. Note 4: A case without sample & hold function turn OAD frequency into 250 kHz or more in addition to a limit of Note 3. A case with sample & hold function turn OAD frequency into 1MHz or more in addition to a limit of Note 3. Table 1.5.4. D-A Conversion Characteristics (Note 1) Symbol - - tsu RO IVREF Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Measuring condition Standard Min. Typ. Max. 8 1.0 3 20 1.5 Unit Bits % s k mA 4 (Note 2) 10 Note 1: Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. Note 2: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "0016". The A-D converter's ladder resistance is not included. Also, when D-A register contents are not "0016", the current IVREF always flows even though Vref may have been set to be unconnected by the A-D control register. Rev.1.10 2003.05.28 page 22 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics Table 1.5.5. Flash Memory Version Electrical Characteristics (Note 1) 100 times guarantee article Symbol - - - - tPS Parameter Word program time Block erase time Erase all unlocked blocks time Lock bit program time Flash memory circuit stabilization wait time Measuring condition Min. Standard Typ. 30 1 1Xn 30 Max 200 4 4Xn 200 15 Unit s s s s s Note 1: Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 C unless otherwise specified. Note 2: n denotes the number of block erases. Table 1.5.6. Flash Memory Version Electrical Characteristics (Note 1) 10,000 times guarantee article (block1 and block A(Note 3)) Standard Symbol Measuring condition Parameter Unit Min. Typ. Max - - - - tPS Word program time Block erase time Erase all unlocked blocks time Lock bit program time Flash memory circuit stabilization wait time 30 1 1Xn 30 T.B.D T.B.D T.B.D T.B.D 15 s s s s s Note 1: Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 C unless otherwise specified. Note 2: n denotes the number of block erases. Note 3: Shown here are the rated values for block 1 and block A when they have been programmed and erased more than 1,000 times. The rated values up to 1,000 times of programming and erasure are the same for all blocks as those products that are guaranteed of 100 times of programming and erasure. Table 1.5.7. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60oC) Flash program, erase voltage VCC1 = 3.3 V 0.3 V or 5.0 V 0.5 V Flash read operation voltage VCC1=2.7 to 5.5 V Rev.1.10 2003.05.28 page 23 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics Table 1.5.8. Low Voltage Detection Circuit Electrical Characteristics (Note 1) Symbol Vdet4 Vdet3 Vdet3s Vdet3r Vdet2 Parameter Voltage down detection voltage (Note 1) Reset level detection voltage (Notes 1, 2) Low voltage reset retention voltage Low voltage reset release voltage (Note 3) RAM retention limit detection voltage (Note 1) Measuring condition Min. 3 .3 2 .2 Standard Typ. 3 .8 2 .8 Max. 4 .4 3 .6 Unit V V V VCC1=0.8 to 5.5V 0 .8 2 .2 1.4 2 .9 2 .0 4 .0 2 .7 V V Note 1: Vdet4 > Vdet3 > Vdet2 Note 2: Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the operation at f(BCLK) 10MHz is guaranteed. Note 3: Vdet3r > Vdet3 is not guaranteed. Table 1.5.9. Power Supply Circuit Timing Characteristics Symbol td(P-R) td(R-S) td(W-S) td(M-L) td(S-R) td(E-A) Parameter Time for internal power supply stabilization during powering-on STOP release time Low power dissipation mode wait mode release time Time for internal power supply stabilization when main clock oscillation starts Hardware reset 2 release wait time Low voltage detection circuit operation start time Measuring condition Min. Standard Typ. Max. 2 150 150 50 Unit ms s s s ms s VCC1=2.7 to 5.5V VCC1=Vdet3r to 5.5V VCC1=2.7 to 5.5V 6 (Note) 20 20 Note : When VCC1 = 5V VCC1 Vdet3r td(S-R) Interrupt for stop mode release CPU clock td(R-S) Rev.1.10 2003.05.28 page 24 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Table 1.5.10. Electrical Characteristics (Note 1) Symbol Parameter HIGH output P60 to P67,P72 to P77,P80 to P84,P86,P87,P90 to P97, IOH=-5mA voltage P100 to P107,P110 to P117,P140,P141 P00 to P07,P10 to P17,P20 to P27,P30 to P37, IOH=-5mA(Note 2) P40 to P47,P50 to P57,P120 to P127,P130 to P137 HIGH output P60 to P67,P72 to P77,P80 to P84,P86,P87,P90 to P97, IOH=-200A voltage P100 to P107,P110 to P117,P140,P141 P00 to P07,P10 to P17,P20 to P27,P30 to P37, IOH=-200A(Note 2) P40 to P47,P50 to P57,P120 to P127,P130 to P137 IOH=-1mA HIGHPOWER HIGH output voltage XOUT IOH=-0.5mA LOWPOWER HIGH output voltage XCOUT HIGHPOWER LOWPOWER Measuring condition Min. VCC1-2.0 VCC2-2.0 VCC1-0.3 VCC2-0.3 VCC1-2.0 VCC1-2.0 Standard Typ. Max. VCC1 Unit V VOH VCC2 VCC1 V VCC2 VCC1 VCC1 2.5 1 .6 2 .0 V 2 .0 0.45 V 0.45 2.0 2 .0 0 0 V V V V VOH VOH With no load applied With no load applied VOL LOW output P60 to P67,P70 to P77,P80 to P84,P86,P87,P90 to P97, IOL=5mA voltage P100 to P107,P110 to P117,P140,P141 P00 to P07,P10 to P17,P20 to P27,P30 to P37, IOL=5mA(Note 2) P40 to P47,P50 to P57,P120 to P127,P130 to P137 LOW output P60 to P67,P70 to P77,P80 to P84,P86,P87,P90 to P97, IOL=200A P100 to P107,P110 to P117,P140,P141 voltage P00 to P07,P10 to P17,P20 to P27,P30 to P37, IOL=200A(Note 2) P40 to P47,P50 to P57,P120 to P127,P130 to P137 IOL=1mA HIGHPOWER XOUT LOW output voltage IOL=0.5mA LOWPOWER LOW output voltage Hysteresis XCOUT HIGHPOWER LOWPOWER VOL VOL With no load applied With no load applied VT+-VT- HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL, SDA, CLK0 to CLK4,TA2OUT to TA4OUT, KI0 to KI3, RxD0 to RxD2, SIN3, SIN4 RESET P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P70 to P77, P80 to P87,P90 to P97,P100 to P107,P110 to P117, P120 to P127,P130 to P137,P140,P141, XIN, RESET, CNVss, BYTE P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P70 to P77, P80 to P87,P90 to P97,P100 to P107,P110 to P117, P120 to P127,P130 to P137,P140,P141, XIN, RESET, CNVss, BYTE P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P72 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107, P110 to P117,P120 to P127,P130 to P137,P140,P141 XIN XCIN At stop mode 0 .2 1 .0 V VT+-VT- Hysteresis HIGH input current 0 .2 2 .2 V IIH VI=5V 5 .0 A LOW input current IIL VI=0V -5.0 A RPULLUP Pull-up resistance VI=0V 30 50 170 k RfXIN RfXCIN VRAM Feedback resistance Feedback resistance RAM retention voltage 1.5 15 2 .0 M M V Note 1: Referenced to VCC=VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=24MHz unless otherwise specified. Note 2: Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on the VCC2 port side. Rev.1.10 2003.05.28 page 25 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Table 1.5.11. Electrical Characteristics (2) (Note 1) Symbol Parameter In single-chip mode, the output pins are open and other pins are VSS Mask ROM Measuring condition f(BCLK)=24MHz, No division, PLL operation No division, Ring oscillation Flash memory Min. Standard Typ. 14 1 18 1.8 15 25 25 Max. 20 Unit mA mA f(BCLK)=24MHz, No division, PLL operation No division, Ring oscillation 27 mA mA mA mA A Flash memory Program Flash memory Erase Mask ROM f(BCLK)=10MHz, VCC1=5.0V f(BCLK)=10MHz, VCC1=5.0V f(XCIN)=32kHz, Low power dissipation mode, ROM(Note 3) f(BCLK)=32kHz, Low power dissipation mode, RAM(Note 3) f(BCLK)=32kHz Low power dissipation mode, Flash memory(Note 3) Ring oscillation, Wait mode f(BCLK)=32kHz, Wait mode (Note 2), ICC Power supply current (VCC1=4.0 to 5.5V) Flash memory 25 A 420 A A A 50 7.5 Mask ROM Flash memory Oscillation capacity High f(BCLK)=32kHz, Wait mode(Note 2), Oscillation capacity Low Stop mode, Topr=25C 2 .0 0.8 0.7 1 .2 1 .1 3.0 4 8 6 A A A A A Idet4 Idet3 Idet2 Voltage down detection dissipation current (Note 4) Reset area detection dissipation current (Note 4) RAM retention limit detection dissipation current (Note 4) Note 1: Referenced to VCC=VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=24MHz unless otherwise specified. Note 2: With one timer operated using fC32. Note 3: This indicates the memory in which the program to be executed exists. Note 4: Idet is dissipation current when the following bit is set to "1" (detection circuit enabled). Idet4: VC27 bit of VCR2 register Idet3: VC26 bit of VCR2 register Idet2: VC25 bit of VCR2 register Rev.1.10 2003.05.28 page 26 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.12. External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 62.5 25 25 15 15 Unit ns ns ns ns ns Table 1.5.13. Memory Expansion Mode and Microprocessor Mode Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA ) Parameter Data input access time (for setting with no wait) Data input access time (for setting with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time Standard Max. Min. (Note 1) (Note 2) (Note 3) 40 30 40 0 0 0 40 Unit ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) - 45 [ns] Note 2: Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 45 f(BCLK) [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. Note 3: Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 45 f(BCLK) [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. Rev.1.10 2003.05.28 page 27 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.14. Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 Unit ns ns ns Table 1.5.15. Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns Table 1.5.16. Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Min. Standard Max. Unit ns ns ns 200 100 100 Table 1.5.17. Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 100 100 Unit ns ns Table 1.5.18. Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns Table 1.5.19. Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time Parameter Standard Max. Min. 800 200 200 Unit ns ns ns Rev.1.10 2003.05.28 page 28 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.20. Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns Table 1.5.21. Timer B Input (Pulse Period Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 1.5.22. Timer B Input (Pulse Width Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 1.5.23. A-D Trigger Input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 1.5.24. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 200 100 100 80 0 30 90 Max. Unit ns ns ns ns ns ns ns Table 1.5.25. External Interrupt INTi Input Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 250 250 Max. Unit ns ns Rev.1.10 2003.05.28 page 29 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.26. Memory Expansion and Microprocessor Modes (for setting with no wait) Standard Measuring condition Symbol Parameter Unit Min. Max. td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK)(Note 3) Data output delay time (refers to WR) Data output hold time (refers to WR)(Note 3) 0.5 X 109 f(BCLK) 25 4 0 (Note 2) 25 4 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.5.1 -4 25 0 25 0 40 4 (Note 1) (Note 2) Note 1: Calculated according to the BCLK frequency as follows: - 40 [ns] f(BCLK) is 12.5MHZ or less. Note 2: Calculated according to the BCLK frequency as follows: 0.5 X 109 - 10 f(BCLK) [ns] Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC2 / VCC2) = 6.7ns. P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF R DBi C Figure 1.5.1. Ports P0 to P10 Measurement Circuit Rev.1.10 2003.05.28 page 30 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.27. Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK)(Note 3) Data output delay time (refers to WR) Data output hold time (refers to WR)(Note 3) (n-0.5) X 109 - 40 f(BCLK) Measuring condition Standard Min. Max. 25 4 0 (Note 2) 25 4 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.5.1 -4 25 0 25 0 40 4 (Note 1) (Note 2) Note 1: Calculated according to the BCLK frequency as follows: [ns] n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n=1, f(BCLK) is 12.5MHZ or less. Note 2: Calculated according to the BCLK frequency as follows: 0.5 X 109 - 10 f(BCLK) [ns] Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC2 / VCC2) = 6.7ns. R DBi C Rev.1.10 2003.05.28 page 31 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.28. Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) Parameter Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) Chip select output hold time (refers to RD) Chip select output hold time (refers to WR) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK) Data output delay time (refers to WR) Data output hold time (refers to WR) ALE signal output delay time (refers to BCLK) ALE signal output hold time (refers to BCLK) ALE signal output delay time (refers to Address) ALE signal output hold time (refers to Adderss) RD signal output delay from the end of Adress WR signal output delay from the end of Adress Address output floating start time 0.5 X 109 f(BCLK) Measuring condition Standard Min. Max. 25 4 (Note 1) (Note 1) Unit ns ns ns ns 25 4 (Note 1) (Note 1) ns ns ns ns ns ns ns ns ns ns ns 25 0 25 0 40 4 (Note 2) (Note 1) Figure 1.5.1 25 -4 (Note 3) (Note 4) ns ns ns ns ns ns 0 0 8 ns ns Note 1: Calculated according to the BCLK frequency as follows: -10 [ns] Note 2: Calculated according to the BCLK frequency as follows: (n-0.5) X 109 f(BCLK) -40 [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. Note 3: Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) -25 [ns] Note 4: Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) -15 [ns] Rev.1.10 2003.05.28 page 32 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode TAiIN input tsu(TAIN-TAOUT) TAiOUT input tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input Figure 1.5.2. Timing Diagram (1) Rev.1.10 2003.05.28 page 33 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q) Figure 1.5.3. Timing Diagram (2) Rev.1.10 2003.05.28 page 34 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) VCC1 = VCC2 = 5V BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD) HLDA output td(BCLK-HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi-Z td(BCLK-HLDA) Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register. Measuring conditions : * VCC1=VCC2=5V * Input timing voltage : Determined with VIL=1.0V, VIH=4.0V * Output timing voltage : Determined with VOL=2.5V, VOH=2.5V Figure 1.5.4. Timing Diagram (3) Rev.1.10 2003.05.28 page 35 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 X tcyc-45)ns.max Hi-Z DB tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) tcyc= 1 f(BCLK) th(WR-DB) (0.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 1.5.5. Timing Diagram (4) Rev.1.10 2003.05.28 page 36 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (1.5 X tcyc-45)ns.max DB Hi-Z th(RD-DB) tSU(DB-RD) 40ns.min 0ns.min Write timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) tcyc= 1 f(BCLK) (0.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc-10)ns.min Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 1.5.6. Timing Diagram (5) Rev.1.10 2003.05.28 page 37 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access ) Read timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (2.5 X tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(WR-AD) th(BCLK-ALE) -4ns.min (0.5 X tcyc )ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DB Hi-Z td(DB-WR) (1.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc )ns.min tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V Figure 1.5.7. Timing Diagram (6) Rev.1.10 2003.05.28 page 38 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access ) Read timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (3.5 X tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 X tcyc )ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DB Hi-Z td(DB-WR) (2.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc )ns.min tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 1.5.8. Timing Diagram (7) Rev.1.10 2003.05.28 page 39 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplex bus selection) Read timing BCLK td(BCLK-CS) 25ns.max tcyc th(RD-CS) (0.5 X tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 X tcyc-25)ns.min th(ALE-AD) (0.5 X tcyc-15)ns.min ADi /DBi Address tdZ(RD-AD) 8ns.max Data input tac3(RD-DB) tSU(DB-RD) 40ns.min Address th(RD-DB) 0ns.min (1.5 X tcyc-45)ns.max td(AD-RD) td(BCLK-AD) 25ns.max 0ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 X tcyc-10)ns.min td(BCLK-RD) 25ns.max ALE th(BCLK-RD) 0ns.min RD Write timing BCLK td(BCLK-CS) 25ns.max tcyc th(WR-CS) (0.5 X tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min ADi /DBi td(AD-ALE) Address Data output td(DB-WR) (1.5 X tcyc-40)ns.min Address th(WR-DB) (0.5 X tcyc-10)ns.min (0.5 X tcyc-25)ns.min td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(AD-WR) 0ns.min th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 1.5.9. Timing Diagram (8) Rev.1.10 2003.05.28 page 40 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 5V) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection ) Read timing tcyc BCLK th(RD-CS) td(BCLK-CS) 25ns.max (0.5 X tcyc )ns.min th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 X tcyc-25)ns.min th(ALE-AD) (0.5 X tcyc-15)ns.min ADi /DB ADi BHE (no multiplex) 25ns.max Address td(BCLK-AD) tdZ(RD-AD) td(AD-RD) 0ns.min 8ns.max Data input th(RD-DB) tac3(RD-DB) (2.5 X tcyc-45)ns.max tSU(DB-RD) 40ns.min 0ns.min th(BCLK-AD) 4ns.min td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 X tcyc )ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD Write timing tcyc BCLK th(WR-CS) td(BCLK-CS) 25ns.max (0.5 X tcyc )ns.min th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min ADi /DB td(AD-ALE) Address Data output td(DB-WR) (2.5 X tcyc-40)ns.min (0.5 X tcyc-25)ns.min th(WR-DB) (0.5 X tcyc )ns.min td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE (no multiplex) td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) (0.5 X tcyc )ns.min 0ns.min ALE td(BCLK-WR) WR, WRL WRH tcyc= 1 f(BCLK) 25ns.max th(BCLK-WR) 0ns.min Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 1.5.10. Timing Diagram (9) Rev.1.10 2003.05.28 page 41 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 = VCC2 = 3V Table 1.5.29. Electrical Characteristics (Note) Symbol VOH HIGH output voltage Parameter P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P72 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107, P110 to P117,P120 to P127,P130 to P137,P140,P141 XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER Measuring condition Min. VCC-0.5 Standard Typ. Max. VCC Unit IOH=-1mA V VOH HIGH output voltage HIGH output voltage LOW output voltage IOH=-0.1mA IOH=-50A With no load applied With no load applied VCC-0.5 VCC-0.5 2 .5 1 .6 VCC VCC V V VOL P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P70 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107, P110 to P117,P120 to P127,P130 to P137,P140,P141 XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER IOL=1mA 0 .5 V VOL LOW output voltage LOW output voltage Hysteresis IOL=0.1mA IOL=50A With no load applied With no load applied 0 0 0 .5 0 .5 V V VT+-VT- HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL, SDA, CLK0 to CLK4, TA2OUT to TA4OUT, KI0 to KI3, RxD0 to RxD2, SIN3,SIN4 RESET P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P70 to P77, P80 to P87,P90 to P97,P100 to P107,P110 to P117, P120 to P127,P130 to P137,P140,P141, XIN, RESET, CNVss, BYTE 0 .2 0 .8 V VT+-VT- Hysteresis HIGH input current 0 .2 (0.7) 1 .8 V IIH VI=3V 4 .0 A LOW input current IIL P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P70 to P77, P80 to P87,P90 to P97,P100 to P107,P110 to P117, P120 to P127,P130 to P137,P140,P141, XIN, RESET, CNVss, BYTE VI=0V -4.0 A RPULLUP Pull-up resistance P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P72 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107, P110 to P117,P120 to P127,P130 to P137,P140,P141 XIN XCIN VI=0V 50 100 3.0 25 500 k M M V RfXIN RfXCIN VRAM Feedback resistance Feedback resistance RAM retention voltage At stop mode 2 .0 Note 1 : Referenced to VCC=VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=10MHz unless otherwise specified. Note 2 : VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13. Rev.1.10 2003.05.28 page 42 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 = VCC2 = 3V Table 1.5.30. Electrical Characteristics (2) (Note 1) Symbol Parameter In single-chip mode, the output pins are open and other pins are VSS Mask ROM Measuring condition f(BCLK)=10MHz, No division No division, Ring oscillation Flash memory Min. Standard Typ. 8 1 8 1 .8 12 22 25 Max. 11 Unit mA mA f(BCLK)=10MHz, No division No division, Ring oscillation 13 mA mA mA mA A Flash memory Program Flash memory Erase Mask ROM f(BCLK)=10MHz, Vcc1=3.0V f(BCLK)=10MHz, Vcc1=3.0V f(XCIN)=32kHz, Low power dissipation mode, ROM(Note 3) f(BCLK)=32kHz, Low power dissipation mode, RAM(Note 3) f(BCLK)=32kHz, Low power dissipation mode, Flash memory(Note 3) Ring oscillation, Wait mode f(BCLK)=32kHz, Wait mode (Note 2), ICC Power supply current (VCC1=2.7 to 3.6V) Flash memory 25 A 420 A A A 45 6.0 Mask ROM Flash memory Oscillation capacity High f(BCLK)=32kHz, Wait mode (Note 2), Oscillation capacity Low Stop mode, Topr=25C 1.8 0 .7 0.6 0 .4 0 .9 3 .0 4 2 4 A A A A A Idet4 Idet3 Idet2 Voltage down detection dissipation current (Note 4) Reset level detection dissipation current (Note 4) RAM retention limit detection dissipation current (Note 4) Note 1: Referenced to VCC=VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=10MHz unless otherwise specified. Note 2: With one timer operated using fC32. Note 3: This indicates the memory in which the program to be executed exists. Note 4: Idet is dissipation current when the following bit is set to "1" (detection circuit enabled). Idet4: VC27 bit of VCR2 register Idet3: VC26 bit of VCR2 register Idet2: VC25 bit of VCR2 register Rev.1.10 2003.05.28 page 43 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 = VCC2 = 3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.31. External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 100 40 40 18 18 Unit ns ns ns ns ns Table 1.5.32. Memory Expansion and Microprocessor Modes Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA ) Parameter Data input access time (for setting with no wait) Data input access time (for setting with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time Standard Max. Min. (Note 1) (Note 2) (Note 3) 50 40 50 0 0 0 40 Unit ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) - 60 [ns] Note 2: Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 60 f(BCLK) [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. Note 3: Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 60 f(BCLK) [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. Rev.1.10 2003.05.28 page 44 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 = VCC2 = 3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.33. Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 150 60 60 Unit ns ns ns Table 1.5.34. Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 600 300 300 Unit ns ns ns Table 1.5.35. Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. 300 150 150 Max. Unit ns ns ns Table 1.5.36. Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 150 Unit ns ns Table 1.5.37. Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Max. Min. 3000 1500 1500 600 600 Unit ns ns ns ns ns Table 1.5.38. Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time Parameter Standard Max. Min. 2 500 500 Unit s ns ns Rev.1.10 2003.05.28 page 45 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 = VCC2 = 3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.39. Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 150 60 60 300 120 120 Max. Unit ns ns ns ns ns ns Table 1.5.40. Timer B Input (Pulse Period Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 1.5.41. Timer B Input (Pulse Width Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 1.5.42. A-D Trigger Input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1500 200 Max. Unit ns ns Table 1.5.43. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 300 150 150 160 0 50 90 Max. Unit ns ns ns ns ns ns ns Table 1.5.44. External Interrupt INTi Input Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 380 380 Max. Unit ns ns Rev.1.10 2003.05.28 page 46 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.45. Memory Expansion, Microprocessor Modes (for setting with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK)(Note 3) Data output delay time (refers to WR) Data output hold time (refers to WR)(Note 3) 0.5 X 109 - 40 f(BCLK) Measuring condition Standard Min. Max. 30 4 0 (Note 2) 30 4 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.5.11 -4 30 0 30 0 40 4 (Note 1) (Note 2) Note 1: Calculated according to the BCLK frequency as follows: [ns] f(BCLK) is 12.5MHZ or less. Note 2: Calculated according to the BCLK frequency as follows: 0.5 X 109 - 10 f(BCLK) [ns] Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC2 / VCC2) = 6.7ns. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF Figure 1.5.11. Ports P0 to P10 Measurement Circuit Rev.1.10 2003.05.28 page 47 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 1.5.46. Memory expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK)(Note 3) Data output delay time (refers to WR) Data output hold time (refers to WR)(Note 3) (n-0.5) X 109 - 40 f(BCLK) Measuring condition Standard Min. Max. 30 4 0 (Note 2) 30 4 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.5.11 -4 30 0 30 0 40 4 (Note 1) (Note 2) Note 1: Calculated according to the BCLK frequency as follows: [ns] n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n=1, f(BCLK) is 12.5MHZ or less. Note 2: Calculated according to the BCLK frequency as follows: 0.5 X 109 - 10 f(BCLK) [ns] Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC2 / VCC2) = 6.7ns. R DBi C Rev.1.10 2003.05.28 page 48 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC, unless otherwise specified) Table 1.5.47. Memory expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Standard Measuring condition Parameter Unit Symbol Min. Max. td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) Chip select output hold time (refers to RD) Chip select output hold time (refers to WR) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK) Data output delay time (refers to WR) Data output hold time (refers to WR) ALE signal output delay time (refers to BCLK) ALE signal output hold time (refers to BCLK) ALE signal output delay time (refers to Address) ALE signal output hold time (refers to Adderss) RD signal output delay from the end of Address WR signal output delay from the end of Address Address output floating start time 0.5 X 109 f(BCLK) 4 (Note 1) (Note 1) 50 ns ns ns ns 50 4 (Note 1) (Note 1) ns ns ns ns ns ns ns ns ns ns ns 40 Figure 1.5.11 0 40 0 50 4 (Note 2) (Note 1) 40 -4 (Note 3) (Note 4) ns ns ns ns ns ns 0 0 8 ns ns Note 1: Calculated according to the BCLK frequency as follows: -10 [ns] Note 2: Calculated according to the BCLK frequency as follows: (n-0.5) X 109 -50 f(BCLK) [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. Note 3: Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) -40 [ns] Note 4: Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) -15 [ns] Rev.1.10 2003.05.28 page 49 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode TAiIN input tsu(TAIN-TAOUT) TAiOUT input tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input Figure 1.5.12. Timing Diagram (1) Rev.1.10 2003.05.28 page 50 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q) Figure 1.5.13. Timing Diagram (2) Rev.1.10 2003.05.28 page 51 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD) HLDA output td(BCLK-HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi-Z td(BCLK-HLDA) Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit of PM0 register and PM11 bit of PM1 register. Measuring conditions : * VCC1=VCC2=3V * Input timing voltage : Determined with VIL=0.6V, VIH=2.4V * Output timing voltage : Determined with VOL=1.5V, VOH=1.5V Figure 1.5.14. Timing Diagram (3) Rev.1.10 2003.05.28 page 52 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 X tcyc-60)ns.max Hi-Z DB tSU(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) tcyc= 1 f(BCLK) (0.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc-10)ns.min Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 1.5.15. Timing Diagram (4) Rev.1.10 2003.05.28 page 53 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (1.5 X tcyc-60)ns.max DB Hi-Z th(RD-DB) tSU(DB-RD) 50ns.min 0ns.min Write timing BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) (0.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc-10)ns.min tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 1.5.16. Timing Diagram (5) Rev.1.10 2003.05.28 page 54 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access) Read timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (2.5 X tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(WR-AD) th(BCLK-ALE) -4ns.min (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DB Hi-Z td(DB-WR) (1.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc-10)ns.min tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 1.5.17. Timing Diagram (6) Rev.1.10 2003.05.28 page 55 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) Read timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (3.5 X tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DB Hi-Z td(DB-WR) (2.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc-10)ns.min tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 1.5.18. Timing Diagram (7) Rev.1.10 2003.05.28 page 56 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (For 2-wait setting, external area access and multiplex bus selection) Read timing BCLK td(BCLK-CS) 40ns.max tcyc th(RD-CS) (0.5 X tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 X tcyc-40)ns.min th(ALE-AD) (0.5 X tcyc-15)ns.min ADi /DBi Address tdZ(RD-AD) 8ns.max Data input tac3(RD-DB) tSU(DB-RD) 50ns.min Address th(RD-DB) 0ns.min (1.5 X tcyc-60)ns.max td(AD-RD) td(BCLK-AD) 40ns.max 0ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-RD) 40ns.max th(BCLK-RD) 0ns.min RD Write timing BCLK td(BCLK-CS) 40ns.max tcyc th(WR-CS) (0.5 X tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 50ns.max th(BCLK-DB) 4ns.min ADi /DBi td(AD-ALE) Address Data output td(DB-WR) (1.5 X tcyc-50)ns.min Address th(WR-DB) (0.5 X tcyc-10)ns.min (0.5 X tcyc-40)ns.min td(BCLK-AD) 40ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min td(AD-WR) 0ns.min th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 40ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 1.5.19. Timing Diagram (8) Rev.1.10 2003.05.28 page 57 of 61 M16C/62 Group (M16C/62P) Electrical Characteristics (Vcc1 = Vcc2 = 3V) VCC1 VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection) Read timing tcyc BCLK th(RD-CS) td(BCLK-CS) 40ns.max (0.5 X tcyc-10)ns.min th(BCLK-CS) 6ns.min CSi td(AD-ALE) (0.5 X tcyc-40)ns.min th(ALE-AD) (0.5 X tcyc-15)ns.min Data input ADi /DB ADi BHE (No multiplex) 40ns.max Address td(BCLK-AD) tdZ(RD-AD) td(AD-RD) 0ns.min 8ns.max th(RD-DB) tac3(RD-DB) (2.5 X tcyc-60)ns.max tSU(DB-RD) 50ns.min 0ns.min th(BCLK-AD) 4ns.min td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-RD) 40ns.max th(BCLK-RD) 0ns.min RD Write timing tcyc BCLK th(WR-CS) td(BCLK-CS) 40ns.max (0.5 X tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 50ns.max th(BCLK-DB) 4ns.min ADi /DB td(AD-ALE) Address Data output td(DB-WR) (2.5 X tcyc-50)ns.min (0.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc-10)ns.min td(BCLK-AD) 40ns.max th(BCLK-AD) 4ns.min ADi BHE (No multiplex) td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) (0.5 X tcyc-10)ns.min 0ns.min ALE td(BCLK-WR) WR, WRL WRH 1 f(BCLK) 40ns.max th(BCLK-WR) 0ns.min tcyc= Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 1.5.20. Timing Diagram (9) Rev.1.10 2003.05.28 page 58 of 61 M16C/62 Group (M16C/62P) Package Dimensions Package Dimensions 100P6S-A MMP JEDEC Code - HD D Weight(g) 1.58 Lead Material Alloy 42 Plastic 100pin 1420mm body QFP MD e EIAJ Package Code QFP100-P-1420-0.65 1 80 b2 100 81 I2 Recommended Mount Pad Symbol HE E 30 51 31 50 A L1 A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME F b A1 e y x M L Detail F Dimension in Millimeters Min Nom Max 3.05 - - 0.1 0.2 0 2.8 - - 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 - - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - - - 0.13 0.1 - - 0 10 - 0.35 - - 1.3 - - 14.6 - - 20.6 - - A2 100P6Q-A MMP JEDEC Code - Weight(g) 0.63 Lead Material Cu Alloy c Plastic 100pin 1414mm body LQFP MD e EIAJ Package Code LQFP100-P-1414-0.50 D 100 76 1 75 b2 HD l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 A3 25 51 26 50 A e F A2 L1 x y b2 I2 MD ME M Detail F Lp Rev.1.10 2003.05.28 page 59 of 61 c b x y L Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 - - 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 - - 0.1 - 0 10 - - 0.225 0.9 - - 14.4 - - - - 14.4 HE E A1 ME ME M16C/62 Group (M16C/62P) Package Dimensions 128P6Q-A MMP JEDEC Code - Weight(g) - Lead Material Cu Alloy Plastic 128pin 1420mm body LQFP MD e EIAJ Package Code LQFP128-P-1420-0.50 HD D 128 1 103 102 b2 l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 38 39 64 65 A F A2 L1 e A3 x y b2 I2 MD ME y b L Detail F Lp x M Dimension in Millimeters Min Nom Max 1.4 1.5 1.7 0.125 0.2 0.05 - - 1.4 0.17 0.22 0.27 0.105 0.125 0.175 13.9 14.0 14.1 19.9 20.0 20.1 - 0.5 - 15.8 16.0 16.2 21.8 22.0 22.2 0.35 0.5 0.65 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 - - 0.1 - 0 8 - - 0.225 - 1.0 - - - 14.4 20.4 - - E HE A1 Rev.1.10 2003.05.28 page 60 of 61 c ME M16C/62 Group (M16C/62P) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Rev.1.10 2003.05.28 page 61 of 61 REVISION HISTORY Rev. Date Page 2 4-5 14-19 22 23 24 30 31 30-31 32 30-32 36-39 40-41 42 47 48 47-48 49 47-49 53-56 57-58 M16C/62 Group (M16C/62P) Short Sheet / Data Sheet Description Summary 1.10 Apr/XX/Y03 (Continued) Table 1.1.1 is partly revised. Table 1.1.2 and 1.1.3 is partly revised. SFR is partly revised. "Note 1" is partly revised. Table 1.5.3 is partly revised. Table 1.5.5 is partly revised. Table 1.5.6 is added. Table 1.5.9 is partly revised. Notes 1 and 2 in Table 1.5.26 is partly revised. Notes 1 in Table 1.5.27 is partly revised. Note 3 is added to "Data output hold time(refers to BCLK)" in Table 1.5.26 and 1.5.27. Note 4 is added to "th(ALE-AD)" in Table 1.5.28. Switching Characteristics is partly revised. th(WR-AD) and th(WR-DB) in Figure 1.5.5 to 1.5.8 is partly revised. th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.9 to 1.5.10 is partly revised. Note 2 is added to Table 1.5.29. Notes 1 and 2 in Table 1.5.45 is partly revised. Notes 1 in Table 1.5.46 is partly revised. Note 3 is added to "Data output hold time(refers to BCLK)" in Table 1.5.45 and 1.5.46. Note 4 is added to "th(ALE-AD)" in Table 1.5.47. Switching Characteristics is partly revised. th(WR-AD) and th(WR-DB) in Figure 1.5.15 to 1.5.18 is partly revised. th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.19 to 1.5.20 is partly revised. A-1 |
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